Avionics systems that use multicore processors can see worst-case execution times (WCET) increase by 8-13x versus a single-core implementation. But a solution exists today to help system integrators mitigate the multicore interference that causes such increases in WCET.
Multicore interference occurs when one or more processor cores attempt to access a shared resource that is already in use by another core. The resulting delays can impact determinism, performance, and ultimately safety. A major congestion point is access to shared memory, but I/O, DMA, shared cache, and even the on-chip interconnect can also cause interference.
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